The present invention relates generally to the fabrication of insulated gate field effect transistors and bipolar transistors and more specifically to an improved fabrication process to produce high voltage, high performance bipolar transistors and CMOS devices with doped polysilicon gates.
The simultaneous fabrication of the CMOS devices and complementary bipolar transistors are well known as exemplified by U.S. Pat. No. 3,865,649 to Beasom. The processing steps produce a PNP bipolar transistor having a collector to base breakdown voltage of 33 volts. Similarly the BV.sub.CEO is less than 20 volts. For certain high voltage, high performance applications, the process described in the Beasom patent is not sufficient. Similarly, Beasom suggests and describes the use of aluminum as the gate of the CMOS structures. This unduly increases the surface area required for the formation of the device and the circuit can have unacceptable levels of stray capacitance between the aluminum and the substrate. Since the aluminum for the gate is also used for the first level interconnects, contact apertures have to be formed subsequent to the formation of the gate oxide and prior to the formation of the aluminum. This can increase the contamination of the gate insulator which undesirably affects the MOS characteristics.
The use of doped polycrystalline silicon gates covered by chemical vapor deposited (CVD) silicon oxide for CMOS devices is well known and is described in U.S. Pat. No. 4,075,754 to Cook, Jr. Although showing the process for the formation of a polysilicon gate for an MOS structure, these processing steps use an impurity concentration and temperature levels not compatible with the simultaneous formation of high voltage, high performance bipolar transistors. Thus, there exists a need for a method of fabricating high voltage, high efficiency bipolar transistors and CMOS devices with polysilicon gates.